module cc_reg(
	input				reseti,
	input				mclki,
	//axilite  
	input         arvalid,   
	input [31:0]  araddr,    
	output        arready,   
	input         awvalid,   
	input [31:0]  awaddr,    
	output        awready,   
	output reg        rvalid,    
	output reg [31:0] rdata,     
	input  [1:0]  rresp,     
	input         rready,    
	input         wvalid,    
	input [31:0]  wdata,     
	input [3:0]   wstrb,     
	output        wready    
	);
	
	parameter ADD_ID	= 20'h00000;
	parameter ADD_VER	= 20'h00001;
	parameter ADD_TEST_REG0	= 20'h00002;
	parameter ADD_TEST_REG1	= 20'h00003;
	
 reg [31:0] awaddr_reg;
 wire[31:0] waddr;
 reg [31:0] test_reg0;
 reg [31:0] test_reg1;
 
////////////////////read register//////////////////////////
always@(posedge reseti or posedge mclki)
begin
	if(reseti)begin
		rvalid   <= 0;
		rdata <= 32'b0;
	end else if (arvalid) begin
	  rvalid <= 1'b1;
	  
		case(araddr[19:0])
			ADD_ID		   :	rdata <= 32'h51000000;
			ADD_VER 	   :	rdata <= 32'h00000001;
			ADD_TEST_REG0:	rdata <= test_reg0;
			ADD_TEST_REG1:	rdata <= test_reg1;
		endcase   
	end else if (rready)begin
	  rdata <= 0;
	  rvalid <= 1'b0;		
	end
end

assign arready = 1'b1;




////////////////////write register//////////////////////////
always@(posedge reseti or posedge mclki)
begin
	if(reseti)
		awaddr_reg   <= 0;
	else if(awvalid )
	  awaddr_reg <= awaddr;
end


always@(posedge reseti or posedge mclki)
begin
	if(reseti)begin
		test_reg0 <= 32'b0;
		test_reg1 <= 32'b0;
	end else if (wvalid && wready)begin
		case(waddr[19:0])
			ADD_TEST_REG0:	 test_reg0 <= wdata;
			ADD_TEST_REG1:	 test_reg1 <= wdata;
		endcase   
	end
end
	
assign awready = 1'b1;
assign wready = 1'b1;
assign waddr = (awvalid) ? awaddr : awaddr_reg;


endmodule
